In the prior art, an electronic system for testing chips is disclosed in U.S. Pat. No. 5,390,129. This prior art system is assigned to Unisys Corporation, who also is the assignee of the present invention.
A simplified block diagram of the prior art chip testing system is shown in FIG. 2 of patent ""129. That system includes a computer 50 which is coupled via a time-shared bus 52 to a plurality of driver boards 100; and each driver board 100 is coupled to a respective burn-in board 500 which holds several integrated circuit chips that are to be tested.
In operation, the computer 50 sequentially sends each driver board 100 a separate set of test data patterns that are used to test the chips. These test data patterns are stored on each driver board in a large SRAM which is shown in FIG. 3 by reference numeral 107 and is shown in greater detail in FIG. 9 by reference numeral 145. Which particular driver board receives and stores the test data patterns at any one time is determined by an address circuit 100A that is on the driver board, and is shown in the FIG. 2 block diagram.
After the test data patterns are stored in the SRAM 145 on all of the driver boards 100, then the chips on all of the burn-in boards 500 can be tested in parallel. To do that, the test patterns are concurrently read from all of the SRAMs and sent through respective output driver modules 164, as shown in FIG. 14, to the chips on all of the burn-in boards 500.
One particular feature of the chip testing system in patent ""129 is that each burn-in board includes an ID code which identifies the types of chips that are to be tested on the board. That ID code is sensed by the driver board 100 and sent to the computer 50; and in response, the test data patterns which the computer 50 sends to the driver board are tailored to the ID code that is sensed.
However, the chip testing system in patent ""129 also has some major limitations which are imposed by the FIG. 2 architecture. For example, the computer 50 is the sole source of the test data patterns for all of the driver boards 100. Consequently, the speed of operation of the chip testing system is limited because the computer 50 can only send the test data patterns to a single driver board at a time over the bus 52.
Another limitation of the chip testing system in patent ""129 is that each driver board 100 always tests all of the chips on a burn-in board 500 concurrently. However, each burn-in board inherently has a limit on the total amount of power which the chips on the board can dissipate. Thus, in order to keep the total power dissipation on each burn-in board 500 below a certain limit, the total number of chips on each burn-in board must be decreased as the maximum power dissipation per chip increases.
Still another limitation of the chip testing system in patent ""129 is that the stored test data patterns in a large SRAM 145 on each driver board can make very inefficient use of the SRAM memory cells. FIG. 9 of patent ""129 shows that each SRAM 145 receives nineteen address bits and has eight data output bits; and thus the SRAM 145 on each driver circuit has eight million memory cells. But, certain types of chips are tested by sending them sequences of serial bit streams that vary in number with time. Thus, if an SRAM 145 sends four bit streams during one time interval and sends only two bit streams during other time intervals, then half of the SRAM is wasted when the two bit streams are being sent.
To address the above problems with the chip testing system of patent ""129, the present inventors filed three U.S. patent applications on Aug. 31, 1999 which are identified as follows:
1. U.S. Ser. No. 09/386,946 entitled xe2x80x9cAn Electronic System for Testing Chips Having A Selectable Number Of Pattern Generators That Concurrently Broadcast Different Bit Streams To Selectable Sets Of Chip Driver Circuitsxe2x80x9d;
2. U.S. Ser. No. 09/387,197 entitled xe2x80x9cA Program Storage Device Containing Instructions That Are Spaced Apart By Unused Bits That End On Word Boundaries And Which Generate Chip Testing Bit Streams Of Any Lengthxe2x80x9d; and,
3. U.S. Ser. No. 09/386,945 entitled xe2x80x9cAn Electronic System For Testing A Set Of Multiple Chips Concurrently Or Sequentially In Selectable Subsets Under Program Control To Limit Chip Power Dissipationxe2x80x9d.
Each of the above patent applications include the same set of FIGS. 1-12, and they each have the same Detailed Description. Also, each of the above patent applications has a separate set of claims which cover different aspects of the chip testing system that is disclosed.
The invention as claimed in U.S. Ser. No. 09/386,946 addresses the limitation in patent ""129 regarding speed of operation. In particular, those claims cover a system for testing integrated circuit chips which is comprised of a selectable number of pattern generators, each of which is coupled via a separate bus to a selectable number of chip driver circuits. Each pattern generator also is coupled to a respective memory, which stores different bit streams, word by word, from its respective memory; and it sends the words that are read to all of the chip driver circuits which are coupled to its separate bus, simultaneously. while that is occurring, each chip driver converts the words which it is sent into bit serial test signals which test multiple integrated circuit chips in parallel. Since all the chip driver circuits which are coupled to one separate bus receive the words of the bit streams simultaneously from one pattern generator, the speed of operation is increased over the prior art. Also, since all of the pattern generators send different bit streams at the same time on separate busses, the speed of operation is further increased over the prior art.
In U.S. Ser. No. 09/387,197, the invention as claimed addresses the limitations of patent ""129 regarding inefficient use of memory to store the test data patterns. In particular, these claims cover a system for testing integrated circuit chips which is comprised of a pattern generator that is coupled to a memory which stores variable length instructions that specify sets of bit streams for testing the chips. Each variable length instruction includes a code which indicates the number of bit streams in the set. Each bit stream in the set consists of a selectable number of bits which start on a word boundary and vary in increments of one bit. A respective series of unused bits starts immediately after each bit stream and ends on a word boundary.
If the code indicates that the number of bit streams in a set is only one, then the one bit stream is stored in consecutive words of the memory. If the code indicates the number bit streams in a set is more that one, then those multiple bit streams are stored in an interleaved fashion in consecutive words in the memory. Consequently, the only memory cells that are wasted are those which store the unused bits after each bit stream. But, those unused bits are insignificant in number when each of the bit streams is long.
In U.S. Ser. No. 09/386,945, the invention as claimed addresses the limitations of patent ""129 regarding total power dissipation by the chips which being tested on the burn-in board. In particular, those claims cover a system for testing integrated circuit chips which is comprised of a signal generator that generates a clock signal; and a control circuit having a first input which receives the clock signal, a second input for receiving commands, and multiple outputs. A command source sends programmable sequences of the commands to the second input of the control circuit; and a means in the control circuit selects particular outputs in response to the commands and passing the clock signal from the first input to only the selected outputs
All of the outputs of the control circuit are coupled through respective clock transmitters to different chips which are to be tested. Thus, in response to the programmable commands, the clock signal can be sent sequentially to the chips that are to be tested, in selectable subsets. By such sequencing, the total power dissipation of the chips that are tested can be regulated when the chips are of a type that dissipate a large amount of power when they receive the clock signal, but dissipate substantially less power when they do not receive the clock signal. Such chips include, for example, CMOS microprocessor chips and CMOS memory chips.
Despite all of the features of the chip testing system that is disclosed in the above three patent applications (hereinafter the xe2x80x9cbase systemxe2x80x9d), the present inventors have further discovered a major improvement to that system. By this improved system, the amount of memory which is required to define the test signals for the chips is reduced by several orders of magnitude.
A preferred embodiment of the improved system is described herein and in each of the four related cases that are identified on page 1. In each case, the improved system is described with the same set of Figures and the same Detailed Description. Also, each case has a separate set of claims that cover a different aspect of the improved system.
In order to fully understand the structure and operation of the improved system, it first is necessary to have an understanding of the base system that is described in the three referenced patent applications 09/386,946 and 09/387,197 and 09/386,945. Accordingly, FIGS. 1-12 of those applications, as well as their Detailed Description, are herein repeated. Then, the improved system is described herein in conjunction with FIGS. 13-22, as a modification to the base system of FIGS. 1-12.
The present invention, as claimed covers one particular portion of a system for testing IC chips selectively with a first bit stream that is stored in a memory or a second bit stream that is internally generated. A major benefit which is achieved by generating the second bit stream internally within the system is that the amount of storage which is required in the memory is greatly reduced. For example, the second bit stream might contain a total of one billion bits; but it can be generated with instructions which require less than one thousand bits of storage in the memory.
The particular portion of the system which is claimed as the present invention is an intermediate stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips. This intermediate stage is comprised of a plurality of input address registers which hold respective input addresses; and a memory address generator, coupled to the input address registers, which generates a series of memory addresses by selecting bits from the input addresses. A memory is coupled to the memory address generator, which sequentially receives each memory address in the series; and in response, this memory sends a corresponding series of translated addresses to a memory output. Multiple output registers are coupled to the memory output, and each output register stores a respective translated address in the series.
With this intermediate stage, the input addresses can be virtual addresses in a virtual, or hypothetical, memory; and, those virtual addresses can be translated into physical addresses for an actual memory chip that is to be tested. This feature is particularly useful where several different types of memory chips need to be tested; and where for each chip type, the memory cells are arranged in rows and columns which are addressed by different non-consecutive addresses. To perform the virtual to physical address translation, the memory in the intermediate stage stores all of the physical addresses; and the memory address generator selects bits from the virtual addresses to read the desired physical address from the memory in the intermediate stage.